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Very Low Power CMOS SRAM 1M X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616LV1611
n FEATURES
Y Wide VCC operation voltage : 2.4V ~ 5.5V Y Very low power consumption : VCC = 3.0V Operation current : 46mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25 OC VCC = 5.0V Operation current : 115mA (Max.) at 55ns 10mA (Max.) at 1MHz Standby current : 6.0uA (Typ.) at 25OC Y High speed access time : -55 55ns(Max.) at VCC=3.0~5.5V -70 70ns(Max.) at VCC=2.7~5.5V Y Automatic power down when chip is deselected Y Easy expansion with CE2, CE1 and OE options Y I/O Configuration x8/x16 selectable by LB and UB pin. Y Three state outputs and TTL compatible Y Fully static operation, no clock, no refresh Y Data retention supply voltage as low as 1.5V
n DESCRIPTION
The BS616LV1611 is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,576 by 16 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 1.5uA at 3.0V/25OC and maximum access time of 55ns at 3.0V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE1), active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers. The BS616LV1611 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1611 is available in 48-pin TSOP Type I package and 48-ball BGA package.
n POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY
BS616LV1611FC BS616LV1611TC BS616LV1611FI BS616LV1611TI
OPERATING TEMPERATURE
Commercial +0OC to +70OC Industrial -40OC to +85OC
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
VCC=3.0V 10MHz fMax.
VCC=5.0V
VCC=3.0V
1MHz
VCC=5.0V 10MHz
fMax.
1MHz
50uA
8.0uA
9mA
48mA
113mA
1.5mA
19mA
45mA
BGA-48-0912 TSOP I-48
100uA
16uA
10mA
50mA
115mA
2mA
20mA
46mA
BGA-48-0912 TSOP I-48
n PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE1 DQ0 DQ1 DQ2 DQ3 VCC NC VSS DQ4 DQ5 DQ6 DQ7 A19 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A5 A6 A7 OE UB LB CE2 NC DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A12 A13
n BLOCK DIAGRAM
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4
Address Input Buffer
10 Row Decoder
1024
Memory Array
1024 x 16384
BS616LV1611TC BS616LV1611TI
16384 DQ0 . . . . . . DQ15 . . . . . . 16 Data Input Buffer Data Output Buffer 16 1024 Column Decoder 10 Address Input Buffer Control 16 Column I/O Write Driver Sense Amp
16
1 A B C D E F G H LB D8 D9 VSS VCC D14 D15 A18
2 OE UB D10 D11 D12 D13 A19 A8
3 A0 A3 A5 A17 NC A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE1 D1 D3 D4 D5 WE A11
6 CE2 D0 D2 VCC VSS D6 D7 NC
CE2 CE1 WE OE UB LB VCC VSS
A14 A15 A16 A17 A18 A0 A1 A2 A3 A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS616LV1611
1
Revision 2.3 May. 2006
BS616LV1611
n PIN DESCRIPTIONS
Name
A0-A19 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input
Function
These 20 address inputs select one of the 1,048,576 x 16 bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input DQ0-DQ15 Data Input/Output Ports VCC VSS
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n TRUTH TABLE MODE
Chip De-selected (Power Down)
CE1
H X X L
CE2
X L X H H
WE
X X X H H
OE
X X X H H
LB
X X H L X L
UB
X X H X L L L H L L H
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
High Z High Z High Z High Z High Z DOUT High Z DOUT DIN X DIN High Z High Z High Z High Z High Z DOUT DOUT High Z DIN DIN X ICCSB, ICCSB1 ICCSB, ICCSB1 ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC ICC
Output Disabled L
Read
L
H
H
L
H L L
Write
L
H
L
X
H L
NOTES: H means VIH; L means VIL; X means don't care (Must be VIH or VIL state)
R0201-BS616LV1611
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Revision 2.3 May. 2006
BS616LV1611
n ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG PT IOUT
(1)
n OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
RATING
-0.5(2) to 7.0 -40 to +125 -60 to +150 1.0 20
RANG
Commercial Industrial
AMBIENT TEMPERATURE
0OC to + 70OC -40OC to + 85OC
VCC
2.4V ~ 5.5V 2.4V ~ 5.5V
C C
O
W mA
n CAPACITANCE
(1)
(TA = 25 C, f = 1.0MHz)
O
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. -2.0V in case of AC pulse width less than 30 ns.
1. This parameter is guaranteed and not 100% tested.
n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC(5) ICC1 ICCSB ICCSB1(6) PARAMETER
Power Supply
O
O
TEST CONDITIONS
MIN.
2.4 -0.5(2)
TYP.(1)
--
MAX.
5.5
UNITS
V
Input Low Voltage
--
0.8 VCC+0.3(3)
V
Input High Voltage VIN = 0V to VCC, CE1 = VIH or CE2 = VIL VI/O = 0V to V CC, CE1 = VIH or CE2 = VIL or OE = VIH Output Low Voltage V CC = Max, IOL = 2.0mA
2.2
--
V
Input Leakage Current
--
--
1
uA
Output Leakage Current
--
--
1
uA
--
--
0.4
V
Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current - TTL
V CC = Min, IOH = -1.0mA CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = FMAX(4) CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = 1MHz CE1 = VIH, or CE2 = VIL, IDQ = 0mA CE1VCC-0.2V or CE20.2V, VINV CC-0.2V or VIN0.2V
VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V
2.4
--
-46 115
V
--
--
mA
--
--
2 10
mA
--
-1.5 6.0
1.0 2.0
mA
Standby Current - CMOS
--
16 100
uA
1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICC (MAX.) is 45mA/113mA at VCC=3.0V/5.0V and TA=70OC. 6. ICCSB1(MAX.) is 8.0uA/50uA at VCC=3.0V/5.0V and TA=70OC. R0201-BS616LV1611
3
Revision 2.3 May. 2006
BS616LV1611
n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
SYMBOL VDR ICCDR
(3)
O
O
PARAMETER
VCC for Data Retention
TEST CONDITIONS
CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V
MIN.
1.5
TYP. (1)
--
MAX.
--
UNITS
V
Data Retention Current Chip Deselect to Data Retention Time
--
0.8
8.0
uA
tCDR tR
0 See Retention Waveform tRC (2)
--
--
ns
Operation Recovery Time
--
--
ns
1. VCC=1.5V, TA=25OC and not 100% tested. 2. tRC = Read Cycle Time. 3. ICCDR(Max.) is 6.0uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode VDR1.5V
VCC
VIH
VCC
VCC
tCDR
CE1VCC - 0.2V
tR
VIH
CE1
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VCC
VCC
VDR1.5V
VCC
tCDR
tR
CE20.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM "H" TO "L" MAY CHANGE FROM "L" TO "H" DON'T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM "H" TO "L" WILL BE CHANGE FROM "L" TO "H" CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE "OFF" STATE
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others
Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES
1 TTL Output CL(1)
VCC GND
10%
90%
90% 10%
Rise Time: 1V/ns
Fall Time: 1V/ns
1. Including jig and scope capacitance.
R0201-BS616LV1611
4
Revision 2.3 May. 2006
BS616LV1611
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC=3.0~5.5V) MIN. Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Chip Select to Output High Z (CE1) (CE2) (CE1) (CE2) (LB, UB) (CE1) (CE2) (LB, UB) 55 -----10 10 10 5 ----10 TYP. ---------------MAX. -55 55 55 55 30 ----30 30 30 25 -CYCLE TIME : 70ns (VCC=2.7~5.5V) MIN. 70 -----10 10 10 5 ----10 TYP. ---------------MAX. -70 70 70 70 35 ----35 35 35 30 -ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
O O
DESCRIPTION
UNITS
tAVAX tAVQX tELQV1 tELQV2 tBLQV tGLQV tELQX1 tELQX2 tBLQX tGLQX tEHQZ1 tEHQZ2 tBHQZ tGHQZ tAVQX
tRC tAA tACS1 tACS2 tBA tOE tCLZ1 tCLZ2 tBE tOLZ tCHZ1 tCHZ2 tBDO tOHZ tOH
Data Byte Control to Output High Z (LB, UB) Output Enable to Output High Z Data Hold from Address Change
n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1
(1,2,4)
tRC ADDRESS tOH DOUT tAA tOH
R0201-BS616LV1611
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Revision 2.3 May. 2006
BS616LV1611
READ CYCLE 2
(1,3,4)
CE1 tACS1 CE2 tCLZ DOUT
(5)
tACS2 tCHZ
(5)
READ CYCLE 3
(1, 4)
tRC ADDRESS tAA OE tOE CE1 tCLZ1 CE2 tCLZ2 LB, UB
(5) (5)
tOH
tOLZ tACS1 tOHZ tCHZ
(5)
(1,5)
tACS2
tCHZ2 tBA tBE tBDO
(2,5)
DOUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested.
R0201-BS616LV1611
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Revision 2.3 May. 2006
BS616LV1611
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC=3.0~5.5V) MIN. Write Cycle Time Address Set up Time Address Valid to End of Write Chip Select to End of Write Data Byte Control to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1, WE) (CE2) (LB, UB) 55 0 55 55 25 30 0 0 -25 0 -5 TYP. -------------MAX. --------25 --25 -CYCLE TIME : 70ns (VCC=2.7~5.5V) MIN. 70 0 70 70 30 35 0 0 -30 0 -5 TYP. -------------MAX. --------30 --30 -ns ns ns ns ns ns ns ns ns ns ns ns ns
O O
DESCRIPTION
UNITS
tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX1 tWHAX2 tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWC tAS tAW tCW tBW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW
n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1
(1)
tWC ADDRESS
OE tCW CE1
(5) (11)
tWR1
(3)
CE2
(5)
tCW LB, UB tAW WE tAS tOHZ DOUT
(4,10)
(11)
tBW
tWR2
(3)
tWP
(2)
tDH tDW DIN
R0201-BS616LV1611
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Revision 2.3 May. 2006
BS616LV1611
WRITE CYCLE 2
(1,6)
tWC ADDRESS tCW
(11)
CE1
(5)
CE2 tCW LB, UB
(12) (11)
tBW tAW
tWR
(3)
WE tAS tWHZ DOUT
(4,10)
tWP
(2)
tOW tDW tDH
(8,9)
(7)
(8)
DIN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write. 12. The change of Read/Write cycle must accompany with CE or address toggled.
R0201-BS616LV1611
8
Revision 2.3 May. 2006
BS616LV1611
n ORDERING INFORMATION
BS616LV1611
X
X
Z
YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE F: BGA-48-0912 T: TSOP I-48
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
0.250.05
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
SIDE VIEW
D 3.375
0.1
N 48
D 12.0
E 9.0
D1 5.25
E1 3.75
e 0.75
D1
SOLDER BALL 0.35 0.05
e
VIEW A
48 mini-BGA (9mm x 12mm)
2.625
E0.1
E1
R0201-BS616LV1611
9
Revision 2.3 May. 2006
BS616LV1611
n PACKAGE DIMENSIONS
TSOP I-48 Pin (12mm x 20mm)
R0201-BS616LV1611
10
Revision 2.3 May. 2006
BS616LV1611
n Revision History Revision No. 2.2 History Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 220uA to 100uA at 5.0V 20uA to 16uA at 3.0V C-grade from 110uA to 50uA at 5.0V 10uA to 8.0uA at 3.0V Change I-grade operation temperature range - from -25OC to -40OC Draft Date Jan. 13, 2006 Remark
2.3
May. 25, 2006
R0201-BS616LV1611
11
Revision 2.3 May. 2006

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